The present invention relates to integrated circuit (IC) designs. More particularly, the present invention relates to a method and apparatus for processing physical design data of an IC design.
Signal integrity is rapidly becoming one of the important issues in IC designs, especially in very large scale integration (VLSI) physical designs. As the chip size and performance are increasing while the process feature size is reducing, noise caused by relatively small distance between power supply lines has very strong impact on transistor behavior. Such noise may reduce performance or even introduce logic failures into the IC system. In order to reduce the power supply noise decoupling capacitance allocation is usually employed. Since a power/ground grid has a very large dimension and high density, it is almost impossible to manually allocate decoupling capacitors. Thus, automatic capacitance allocation methods have been developed so as to allocate decoupling capacitors under certain constraints required by the IC design.
The Opus database, available from Cadence Design Systems, Inc. of San Jose, Calif., is a standard format database used for the physical data storage and maintenance of various types of IC designs, such as microprocessors, memory units, and application specific integrated circuits (ASICs). The Opus data format is typically used by Opus applications (and their compatibles) which provide a layout view, manual check, and other interactive operations on the physical data. The Opus database has been widely used by design engineers to draw layout and schematic as well as provide another necessary processing. Using the Opus functionality is advantageous to perform intermediate physical design operations since all physical design data are stored inside a single database and direct access thereto is guaranteed. However, some operations such as decoupling capacitance allocation have not been provided by conventional Opus functionality.
A method for allocating decoupling capacitor cells in an integrated circuit (IC) design, includes (a) obtaining geometrical information of rectangular areas in the IC design, each of the rectangular areas not intersecting any design figure in selected metal layers of the IC design in a design area, (b) determining possible locations for rows of decoupling capacitor cell arrays to be placed in the rectangular areas, a row including a set of cell arrays to be placed across the rectangular areas in a direction of a first coordinate axis of the design area, (c) determining for each possible location a number of decoupling capacitor cells included in the row, and (d) selecting row locations satisfying a certain design rule from among the possible locations in a descending order of the number of the decoupling capacitor cells.